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1/45 may 2002 m28w160bt m28w160bb 16 mbit (1mb x16, boot block) 3v supply flash memory features summary n supply voltage v dd = 2.7v to 3.6v core power supply v ddq = 1.65v to 3.6v for input/output v pp = 12v for fast program (optional) n access time: 70, 85, 90,100ns n programming time 10 m s typical double word programming option n common flash interface 64 bit security code n memory blocks parameter blocks (top or bottom location) main blocks n block protection on two parameter blocks wp for block protection n automatic stand-by mode n program and erase suspend n 100,000 program/erase cycles per block n electronic signature manufacturer code: 20h top device code, m28w160bt: 90h bottom device code, m28w160bb: 91h figure 1. packages fbga tsop48 (n) 12 x 20mm m bga tfbga46 (zb) 6.39 x 6.37mm m bga46 (gb) 6.39 x 6.37mm
m28w160bt, m28w160bb 2/45 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................5 figure 3. tsop connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................6 figure 4. m bga connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. tfbga connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. block addresses. . . . . . . . . . . . . . ...........................................9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a0-a19). . .......................................................10 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....10 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................10 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....10 write enable (w). . . . . . . . . . . . . . . . ........... ....................................10 write protect (wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset (rp). . . .................................................................10 v dd supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....10 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................10 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ss ground. . . . . . . . . . . . . . . . . . . . .......... .....................................10 bus operations. . . . . . . . . . . . . . . . . . . . . . . . ........................................11 read.. . . . . . . .................................................................11 write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................11 output disable. . . . . . . . . . .......................................................11 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....11 reset. . . . . . . .................................................................11 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....11 command interface . . . . . . . . . . .................................................12 read memory array command . . . .................................................12 read status register command. . . . ........... ....................................12 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....12 read cfi query command. . . . . . . . ........... ....................................12 block erase command . . . .......................................................12 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............12 double word program command . . . . . . . . . . . ............................. ..........13 clear status register command. . . . ........... ....................................13 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........13 block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....13 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. read electronic signature. . ........... ....................................14
3/45 m28w160bt, m28w160bb table 5. memory blocks protection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....14 table 6. program, erase times and program/erase endurance cycles . . . . . . ........... ...15 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....16 erase suspend status (bit 6) . . . . . . .......... .....................................16 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . ........................................16 program status (bit 4). . . . . . . . . . . . ........... ....................................16 v pp status (bit 3). . . . . . . . .......................................................16 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....16 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........17 reserved (bit 0). . . . . . . . . . . . . . . . . ........... ....................................17 table 7. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............18 table 8. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....19 table 9. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....19 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............19 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....20 figure 9. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............21 table 12. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . ....22 table 13. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . ....23 figure 11. write ac waveforms, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . ...............25 figure 12. power-up and reset ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....26 table 15. power-up and reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package mechanical . . . . . . . . . . . ........... ....................................27 figure 13. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . 27 table 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . 27 figure 14. m bga46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, bottom view package outline28 table 17. m bga46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, package mechanical data . . . 28 figure 15. m bga46 daisy chain - package connections (top view through package) . ........29 figure 16. m bga46 daisy chain - pcb connections proposal (top view through package) . . . . . 29 figure 17. tfbga46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, bottom view package outline30 table 18. tfbga46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, package mechanical data . . . 30 figure 18. tfbga46 daisy chain - package connections (top view through package) . . . . . . . . 31 figure 19. tfbga46 daisy chain - pcb connections proposal (top view through package). . . . 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........32
m28w160bt, m28w160bb 4/45 table 19. ordering information scheme . . . . . . . . . ....................................32 table 20. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............32 revision history. ..............................................................33 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........33 appendix a. block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 22. top boot block addresses, m28w160bt ....................................34 table 23. bottom boot block addresses, m28w160bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 24. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........35 table 25. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........35 table 26. cfi query system interface information. . . . . . . . . ......................... ...36 table 27. device geometry definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 29. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 appendix c. flowcharts and pseudo codes. . . . . . . . . . . . . . . . . . . . . ...............39 figure 20. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 21. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 22. program suspend & resume flowchart and pseudo code . . . . . . ...............41 figure 23. erase flowchart and pseudo code . . . . ....................................42 figure 24. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . ..........43 appendix d. command interface and program/erase controller state .......44 table 30. write state machine current/next. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5/45 m28w160bt, m28w160bb summary description the m28w160b is a 16 mbit (1 mbit x 16) non-vol- atile flash memory that can be erased electrically at the block level and programmed in-system on a word-by-word basis. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. v ddq allows to drive the i/o pin down to 1.65v. an optional 12v v pp power supply is pro- vided to speed up customer programming. the device features an asymmetrical blocked ar- chitecture. the m28w160b has an array of 39 blocks: 8 parameter blocks of 4 kword and 31 main blocks of 32 kword. m28w160bt has the parameter blocks at the top of the memory ad- dress space while the m28w160bb locates the parameter blocks starting from the bottom. the memory maps are shown in figure 6, block ad- dresses. parameter blocks 0 and 1 can be protected from accidental programming or erasure. each block can be erased separately. erase can be suspend- ed in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the memory is offered in tsop48 (10 x 20mm), m bga46 (6.39 x 6.37mm , 0.75mm pitch) and tfbga46 (6.39 x 6.37mm, 0.75mm pitch) packag- es and is supplied with all the bits erased (set to '1'). figure 2. logic diagram table 1. signal names a0-a19 address inputs dq0-dq15 data input/output e chip enable g output enable w write enable rp reset wp write protect v dd core power supply v ddq power supply for input/output v pp optional supply voltage for fast program & erase v ss ground ai02628 20 a0-a19 w dq0-dq15 v dd m28w160bt m28w160bb e v ss 16 g rp wp v ddq v pp
m28w160bt, m28w160bb 6/45 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 nc dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai02630 m28w160bt m28w160bb 12 1 13 24 25 36 37 48 dq8 nc a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ss
7/45 m28w160bt, m28w160bb figure 4. m bga connections (top view through package) ai02629 c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ss dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp a19
m28w160bt, m28w160bb 8/45 figure 5. tfbga connections (top view through package) ai03804 c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ss dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp a19
9/45 m28w160bt, m28w160bb figure 6. block addresses note: also see appendix a, tables 22 and 23 for a full listing of the block addresses. ai04310 4 kwords fffff ff000 32 kwords 0ffff 08000 32 kwords 07fff 00000 m28w160bt top boot block addresses 4 kwords f8fff f8000 32 kwords f0000 f7fff total of 8 4 kword blocks total of 31 32 kword blocks 4 kwords fffff f8000 32 kwords 32 kwords 00fff 00000 m28w160bb bottom boot block addresses 4 kwords f7fff 0ffff 32 kwords f0000 08000 total of 31 32 kword blocks total of 8 4 kword blocks 07fff 07000
m28w160bt, m28w160bb 10/45 signal descriptions see figure 2 logic diagram and table 1,signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or data to be programmed during a write bus op- eration. chip enable (e). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. output enable (g). the output enable controls data outputs during the bus read operation of the memory. write enable (w). the write enable controls the bus write operation of the memory's command interface. the data and address inputs are latched on the rising edge of chip enable, e, or write en- able, w, whichever occurs first. write protect (wp). write protect is an input to protect or unprotect the two lockable parameter blocks. when write protect is at v il , the lockable blocks are protected and program or erase oper- ations are not possible. when write protect is at v ih , the lockable blocks are unprotected and can be programmed or erased (refer to table 4, mem- ory blocks protection truth). reset (rp). the reset input provides a hard- ware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is mini- mized. when reset is at v ih , the device is in nor- mal operation. exiting reset mode the device enters read array mode, but a negative transition of chip enable or a change of the address is re- quired to ensure valid data outputs. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all out- puts to be powered independently from v dd .v ddq can be tied to v dd or can use a separate supply. v pp program supply voltage. v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin. the supply voltage v dd and the program supply voltage v pp can be applied in any order. if v pp is kept in a low voltage range (0v to 3.6v) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp >v pp1 en- ables these functions (see table 11, dc charac- teristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. if v pp is in the range 11.4v to 12.6v it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is com- pleted (see table 13 and 14). v ss ground. v ss is the reference for all voltage measurements. note: each device in a system should have v dd, v ddq and v pp decoupled with a 0.1 m f ca- pacitor close to the pin. see figure 8, ac mea- surement load circuit. the pcb trace widths should be sufficient to carry the required v pp program and erase currents.
11/45 m28w160bt, m28w160bb bus operations there are six standard bus operations that control the device. these are bus read, bus write, out- put disable, standby, automatic standby and re- set. see table 2, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. read. read bus operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output en- able must be at v il in order to perform a read op- eration. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read de- pends on the previous command written to the memory (see command interface section). see figure 9, read mode ac waveforms, and table 12, read ac characteristics, for details of when the output becomes valid. read mode is the default state of the device when exiting reset or after power-up. write. bus write operations write commands to the memory or latch input data to be programmed. a write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. see figures 10 and 11, write ac waveforms, and tables 13 and 14, write ac characteristics, for details of the timing requirements. output disable. the data outputs are high im- pedance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the de- vice enters standby mode when finished. automatic standby. automatic standby pro- vides a low power consumption state during read mode. following a read operation, the device en- ters automatic standby after 150ns of bus inactiv- ity, even if chip enable is low, v il , and the supply current is reduced to i dd1 . the data inputs/out- puts will still output data. reset. during reset mode, when output enable is low, v il , the memory is deselected and the out- puts are high impedance. the memory is in reset mode when reset is at v il . the power consump- tion is reduced to the standby level, independently from the chip enable, output enable or write en- able inputs. if reset is pulled to v ss during a pro- gram or erase, this operation is aborted and the memory content is no longer valid. table 2. bus operations note: x = v il or v ih ,v pph = 12v 5%. operation e g w rp wp v pp dq0-dq15 read v il v il v ih v ih x don't care data output write v il v ih v il v ih x v dd or v pph data input output disable v il v ih v ih v ih x don't care hi-z standby v ih xx v ih x don't care hi-z reset x x x v il x don't care hi-z
m28w160bt, m28w160bb 12/45 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time, to monitor the progress of an operation, or the program/ erase states. see appendix d, table 30, write state machine current/next, for a summary of the command interface. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 3, commands, in conjunction with the text descriptions below. read memory array command the read command returns the memory to its read mode. one bus write cycle is required to is- sue the read memory array command and return the memory to read mode. subsequent read op- erations will read the addressed location and out- put the data. when a device reset occurs, the memory defaults to read mode. read status register command the status register indicates when a program or erase operation is complete and the success or failure of the operation itself. issue a read status register command to read the status register's contents. subsequent bus read operations read the status register, at any address, until another command is issued. see table 7, status register bits, for details on the definitions of the bits. the read status register command may be is- sued at any time, even during a program/erase operation. any read attempt during a program/ erase operation will automatically output the con- tent of the status register. read electronic signature command the read electronic signature command reads the manufacturer and device codes. the read electronic signature command consists of one write cycle, a subsequent read will output the manufacturer or the device code depending on the levels of a0. the manufacturer code is out- put when the address line a0 is at v il , the device code is output when a0 is at v ih . addresses a1- a7 must be kept to v il , other addresses are ig- nored. the codes are output on dq0-dq7 with dq8-dq15 at 00h. (see table 4) read cfi query command the read query command is used to read data from the common flash interface (cfi) memory area, allowing programming equipment or appli- cations to automatically match their interface to the characteristics of the device. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash interface memory area. see ap- pendix b, common flash interface, tables 24, 25, 26, 27, 28 and 29 for details on the information contained in the common flash interface memory area. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to '1'. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. n the first bus cycle sets up the erase command. n the second latches the block address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. during erase operations the memory will only ac- cept the read status register command and the program/erase suspend command, all other com- mands will be ignored. typical erase times are given in table 6, program, erase times and pro- gram/erase endurance cycles. see appendix c, figure 23, erase flowchart and pseudo code, for the flowchart for using the erase command. program command the memory array can be programmed word-by- word. two bus write cycles are required to issue the program command. n the first bus cycle sets up the program command. n the second latches the address and the data to be written and starts the program/erase controller. during program operations the memory will only accept the read status register command and the program/erase suspend command. all other
13/45 m28w160bt, m28w160bb commands will be ignored. typical program times are given in table 6, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. see appendix c, figure 20, program flowchart and pseudo code, for the flowchart for using the program command. double word program command this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.the two words must differ only for the address a0. programming should not be attempt- ed when v pp is not at v pph . the command can be executed if v pp is below v pph but the result is not guaranteed. three bus write cycles are necessary to issue the double word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations output the status register con- tent after the programming has started. program- ming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c, figure 21, double word pro- gram flowchart and pseudo code, for the flow- chart for using the double word program command. clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to `0'. one bus write cycle is required to issue the clear status register command. the bits in the status register do not automatical- ly return to `0' when a new program or erase com- mand is issued. the error bits in the status register should be cleared before attempting a new program or erase command. program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. one bus write cycle is required to issue the program/erase command and pause the program/erase control- ler. during program/erase suspend the command in- terface will accept the program/erase resume, read array, read status register, read electron- ic signature and read cfi query commands. ad- ditionally, if the suspend operation was erase then the program command will also be accepted. only the blocks not being erased may be read or pro- grammed correctly. during a program/erase suspend, the device can be placed in a pseudo-standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c, figure 22, program suspend & resume flowchart and pseudo code, and figure 24, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the command. once the command is issued subse- quent bus read operations read the status reg- ister. see appendix c, figure 22, program or double word program suspend & resume flowchart and pseudo code, and figure 24, erase suspend & resume flowchart and pseudo code for flow- charts for using the program/erase resume com- mand. block protection two parameter/lockable blocks (blocks #0 and #1) can be protected against program or erase oper- ations. unprotected blocks can be programmed or erased. to protect the two lockable blocks set write pro- tect to v il .whenv pp is below v pplk all blocks are protected. any attempt to program or erase pro- tected blocks will abort, the data in the block will not be changed and the status register outputs the error. table 5, memory blocks protection truth table , defines the protection methods.
m28w160bt, m28w160bb 14/45 table 3. commands note: 1. x = don't care. 2. a0=v il outputs manufacturer code, a0=v ih outputs device code. address a7-a1 must be v il . 3. addr 1 and addr 2 must be consecutive addresses differing only for a0. table 4. read electronic signature note: rp = v ih . table 5. memory blocks protection truth table note: 1. x = don't care 2. v pp must also be greater than the program voltage lock out v pplk . commands no. of cycles bus write operations 1st cycle 2nd cycle 3nd cycle bus op. addr data bus op. addr data bus op. addr data read memory array 1+ write x ffh read read addr data read status register 1+ write x 70h read x status register read electronic signature 1+ write x 90h read signature addr (2) signature read cfi query 1+ write x 98h read cfi addr query erase 2 write x 20h write block addr d0h program 2 write x 40h or 10h write addr data input double word program (3) 3 write x 30h write addr 1 data input write addr 2 data input clear status register 1 write x 50h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h code device e g w a0 a1-a7 a8-a19 dq0-dq15 manufact. code v il v il v ih v il v il don't care 20h device code m28w160bt v il v il v ih v ih v il don't care 90h m28w160bb v il v il v ih v ih v il don't care 91h v pp (1) rp wp (1) lockable blocks (blocks #0 and #1) other blocks x v il x protected protected v il v ih x protected protected v dd or v pph (2) v ih v il protected unprotected v dd or v pph (2) v ih v ih unprotected unprotected
15/45 m28w160bt, m28w160bb table 6. program, erase times and program/erase endurance cycles parameter test condition s m28w160b unit min typ max word program v pp =v dd 10 200 m s double word program v pp =12v 5% 10 200 m s main block program v pp =12v 5% 0.16 5 s v pp =v dd 0.32 5 s parameter block program v pp =12v 5% 0.02 4 s v pp =v dd 0.04 4 s main block erase v pp =12v 5% 110 s v pp =v dd 110 s parameter block erase v pp =12v 5% 0.8 10 s v pp =v dd 0.8 10 s program/erase cycles (per block) 100,000 cycles
m28w160bt, m28w160bb 16/45 status register the status register provides information on the current or previous program or erase operation. the various bits convey information and errors on the operation. to read the status register the read status register command can be issued, re- fer to the read status register command section. to output the contents, the status register is latched on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . either chip enable or output enable must be toggled to update the latched data. bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 7, status register bits. refer to table 7 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low (set to `0'), the program/erase controller is active; when the bit is high (set to `1'), the pro- gram/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high . during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block protection status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit (set to `1') indicates that an erase operation has been suspended or is going to be suspended. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). bit 7 is set within 30 m s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to `1'), the program/ erase controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. the erase sta- tus bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program failure. when the program status bit is high (set to `1'), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v pp becomes invalid during an operation. when the v pp status bit is low (set to `0'), the volt- age on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to `1'), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit (set to `1') indicates that a pro- gram operation has been suspended or is going to be suspended. the program suspend status should only be con- sidered valid when the program/erase controller status bit is high (program/erase controller inac- tive). bit 2 is set within 5 m s of the program/erase suspend command being issued therefore the
17/45 m28w160bt, m28w160bb memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a protected block. when the block protection status bit is high (set to `1'), a program or erase operation has been at- tempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value must be masked. note: refer to appendix c, flowcharts and pseudo codes, for using the status register. table 7. status register bits note: logic level '1' is high, '0' is low. bit name logic level definition 7 p/e.c. status '1' ready '0' busy 6 erase suspend status '1' suspended '0' in progress or completed 5 erase status '1' erase error '0' erase success 4 program status '1' program error '0' program success 3v pp status '1' v pp invalid, abort '0' v pp ok 2 program suspend status '1' suspended '0' in progress or completed 1 block protection status '1' program/erase on protected block, abort '0' no operation to protected blocks 0 reserved
m28w160bt, m28w160bb 18/45 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 8. absolute maximum ratings note: 1. depends on range. symbol parameter value unit min max t a ambient operating temperature (1) 40 85 c t bias temperature under bias 40 125 c t stg storage temperature 55 155 c v io input or output voltage 0.6 v ddq +0.6 v v dd ,v ddq supply voltage 0.6 4.1 v v pp program voltage 0.6 13 v
19/45 m28w160bt, m28w160bb dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 9, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 9. operating and ac measurement conditions figure 7. ac measurement i/o waveform figure 8. ac measurement load circuit table 10. device capacitance note: sampled only, not 100% tested. m28w160bt, m28w160bb parameter 70 85 90 100 units min max min max min max min max v dd supply voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 v v ddq supply voltage (v ddq v dd ) 2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 v ambient operating temperature 40 85 40 85 40 85 40 85 c load capacitance (c l ) 50 50 50 50 pf input rise and fall times 5 5 5 5 ns input pulse voltages 0tov ddq 0tov ddq 0tov ddq 0tov ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ai00610 v ddq 0v v ddq /2 ai00609c v ddq c l c l includes jig capacitance 25k w device under test 0.1 m f v dd 0.1 m f v ddq 25k w symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf
m28w160bt, m28w160bb 20/45 table 11. dc characteristics symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 m a i lo output leakage current 0v v out v ddq 10 m a i dd supply current (read) e=v ss ,g=v ih , f = 5mhz 10 20 ma i dd1 supply current (stand-by or automatic stand-by) e=v ddq 0.2v, rp = v ddq 0.2v 15 50 m a i dd2 supply current (reset) rp = v ss 0.2v 15 50 m a i dd3 supply current (program) program in progress v pp =12v 5% 10 20 ma program in progress v pp =v dd 10 20 ma i dd4 supply current (erase) erase in progress v pp =12v 5% 520ma erase in progress v pp =v dd 520ma i dd5 supply current (program/erase suspend) e=v ddq 0.2v, erase suspended 50 m a i pp program current (read or stand-by) v pp >v dd 400 m a i pp1 program current (read or stand-by) v pp v dd 5 m a i pp2 program current (reset) rp = v ss 0.2v 5 m a i pp3 program current (program) program in progress v pp =12v 5% 10 ma program in progress v pp =v dd 5 m a i pp4 program current (erase) erase in progress v pp =12v 5% 10 ma erase in progress v pp =v dd 5 m a v il input low voltage 0.5 0.4 v v ddq 2.7v 0.5 0.8 v v ih input high voltage v ddq 0.4 v ddq +0.4 v v ddq 2.7v 0.7 v ddq v ddq +0.4 v v ol output low voltage i ol =100 m a, v dd =v dd min, v ddq =v ddq min 0.1 v v oh output high voltage i oh =100 m a, v dd =v dd min, v ddq =v ddq min v ddq 0.1 v v pp1 program voltage (program or erase operations) 1.65 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v pplk program voltage (program and erase lock-out) 1v v lko v dd supply voltage (program and erase lock-out) 2v
21/45 m28w160bt, m28w160bb figure 9. read mode ac waveforms table 12. read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . symbol alt parameter m28w160b unit 70 85 90 100 t avav t rc address valid to next address valid min 70 85 90 100 ns t avqv t acc address valid to output valid max 70 85 90 100 ns t axqx (1) t oh address transition to output transition min 0 0 0 0 ns t ehqx (1) t oh chip enable high to output transition min 0 0 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 20 20 25 30 ns t elqv (2) t ce chip enable low to output valid max 70 85 90 100 ns t elqx (1) t lz chip enable low to output transition min 0 0 0 0 ns t ghqx (1) t oh output enable high to output transition min 0 0 0 0 ns t ghqz (1) t df output enable high to output hi-z max 20 20 25 30 ns t glqv (2) t oe output enable low to output valid max 20 20 30 35 ns t glqx (1) t olz output enable low to output transition min 0 0 0 0 ns dq0-dq15 ai00619 valid a0-a19 e taxqx tavav valid tavqv telqv telqx tglqv tglqx addr. valid chip enable outputs enabled data valid standby g tghqx tghqz tehqx tehqz
m28w160bt, m28w160bb 22/45 figure 10. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid a0-a19 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai03572 twphwh wp twhgl tqvwpl twhel
23/45 m28w160bt, m28w160bb table 13. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w160b unit 70 85 90 100 t avav t wc write cycle time min 70 85 90 100 ns t avwh t as address valid to write enable high min 45 45 50 50 ns t dvwh t ds data valid to write enable high min 45 45 50 50 ns t elwl t cs chip enable low to write enable low min 0 0 0 0 ns t elqv chip enable low to output valid min 70 85 90 100 ns t qvvpl (1,2) output valid to v pp low min 0 0 0 0 ns t qvwpl output valid to write protect low min 0 0 0 0 ns t vphwh (1) t vps v pp high to write enable high min 200 200 200 200 ns t whax t ah write enable high to address transition min 0 0 0 0 ns t whdx t dh write enable high to data transition min 0 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 0 ns t whel write enable high to chip enable low min 25 25 30 30 ns t whgl write enable high to output enable low min 20 20 30 30 ns t whwl t wph write enable high to write enable low min 25 25 30 30 ns t wlwh t wp write enable low to write enable high min 45 45 50 50 ns t wphwh write protect high to write enable high min 45 45 50 50 ns
m28w160bt, m28w160bb 24/45 figure 11. write ac waveforms, chip enable controlled e g dq0-dq15 command cmd or data status register v pp valid a0-a19 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling telqv ai03573 w twpheh wp tehgl tqvwpl
25/45 m28w160bt, m28w160bb table 14. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w160b unit 70 85 90 100 t avav t wc write cycle time min 70 85 90 100 ns t aveh t as address valid to chip enable high min 45 45 50 50 ns t dveh t ds data valid to chip enable high min 45 45 50 50 ns t ehax t ah chip enable high to address transition min 0 0 0 0 ns t ehdx t dh chip enable high to data transition min 0 0 0 0 ns t ehel t cph chip enable high to chip enable low min 25 25 30 30 ns t ehgl chip enable high to output enable low min 25 25 30 30 ns t ehwh t wh chip enable high to write enable high min 0 0 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 50 50 ns t elqv chip enable low to output valid min 70 85 90 100 ns t qvvpl (1,2) output valid to v pp low min 0 0 0 0 ns t qvwpl data valid to write protect low min 0 0 0 0 ns t vpheh (1) t vps v pp high to chip enable high min 200 200 200 200 ns t wlel t cs write enable low to chip enable low min 0 0 0 0 ns t wpheh write protect high to chip enable high min 45 45 50 50 ns
m28w160bt, m28w160bb 26/45 figure 12. power-up and reset ac waveforms table 15. power-up and reset ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initi alization during power up or reset. symbol parameter test conditio n m28w160b unit 70 85 90 100 t phwl t phel t phgl reset high to write enable low, chip enable low, output enable low during program and erase min 50 50 50 50 m s others min 30 30 30 30 ns t plph (1,2) reset low to reset high min 100 100 100 100 ns t vdhph (3) supply voltages high to reset high min 50 50 50 50 m s ai03453b w, rp tphwl tphel tphgl e, g vdd, vddq tvdhph tphwl tphel tphgl tplph power-up reset
27/45 m28w160bt, m28w160bb package mechanical figure 13. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0279 a 0 5 0 5 n48 48 cp 0.10 0.0039 tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
m28w160bt, m28w160bb 28/45 figure 14. m bga46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale table 17. m bga46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, package mechanical data symbol mm inch typ min max typ min max a 1.000 0.0394 a1 0.180 0.0071 a2 0.700 0.0276 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 6.390 6.340 6.440 0.2516 0.2496 0.2535 d1 5.250 0.2067 ddd 0.008 0.0003 e 0.750 0.0295 e 6.370 6.320 6.420 0.2508 0.2488 0.2528 e1 3.750 0.1476 fd 0.570 0.0224 fe 1.310 0.0516 sd 0.375 0.0148 se 0.375 0.0148 e1 e d1 d b a2 a1 a bga-g05 ddd e e fe sd se ball oa1o fd
29/45 m28w160bt, m28w160bb figure 15. m bga46 daisy chain - package connections (top view through package) figure 16. m bga46 daisy chain - pcb connections proposal (top view through package) ai03298 c b a 8 7 6 5 4 3 2 1 e d f ai3299 c b a 8 7 6 5 4 3 2 1 e d f start point end point
m28w160bt, m28w160bb 30/45 figure 17. tfbga46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, bottom view package outline drawing is not to scale. table 18. tfbga46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, package mechanical data e1 e d1 d b a2 a1 a bga-z13 ddd e e fd fe sd se ball oa1o symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.390 6.290 6.490 0.2516 0.2476 0.2555 d1 5.250 0.2067 ddd 0.100 0.0039 e 6.370 6.270 6.470 0.2508 0.2469 0.2547 e 0.750 0.0295 e1 3.750 0.1476 fd 0.570 0.0224 fe 1.310 0.0516 sd 0.375 0.0148 se 0.375 0.0148
31/45 m28w160bt, m28w160bb figure 18. tfbga46 daisy chain - package connections (top view through package) figure 19. tfbga46 daisy chain - pcb connections proposal (top view through package) ai03298 c b a 8 7 6 5 4 3 2 1 e d f ai3299 c b a 8 7 6 5 4 3 2 1 e d f start point end point
m28w160bt, m28w160bb 32/45 part numbering table 19. ordering information scheme table 20. daisy chain ordering scheme note:devices are shipped from the factory with the memory content bits erased to '1'. for a list of available options (speed, package, etc...) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m28w160bt 90 n 6 t device type m28 operating voltage w=v dd = 2.7v to 3.6v; v ddq = 1.65v to 3.6v device function 160b = 16 mbit (x16), boot block array matrix t=topboot b = bottom boot speed 70 = 70 ns 85 = 85 ns 90 = 90 ns 100 = 100 ns package n = tsop48: 12 x 20 mm gb = m bga46: 6.39 x 6.37mm, 0.75 mm pitch zb = tfbga46: 6.39 x 6.37mm, 0.75 mm pitch temperature range 1=0to70 c 6=40to85 c optio n t = tape & reel packing example: m28w160b -gb t device type m28w160b daisy chain -gb = m bga46: 6.39 x 6.37mm, 0.75 mm pitch -zb = tfbga46: 6.39 x 6.37mm, 0.75 mm pitch optio n t = tape & reel packing
33/45 m28w160bt, m28w160bb revision history table 21. document revision history date version revision details july 1999 -01 first issue 9/21/99 -02 parameter block erase typ. specification change added t whgl and t ehgl 10/20/99 -03 m bga package mechanical data change daisy chain diagrams, package and pcb connections, added 2/09/00 -04 access time conditions change reset mode function change to remove power down mode instructions description clarification change of parameter block erase value block protections description clarification security code area definition change i dd2 and i dd3 value change t plrh value change program, erase, command interface flowcharts clarification package mechanical data change m bga package outline diagram change 4/19/00 -05 daisy chain part numbering defined m bga daisy chain diagrams, package and pcb connections re-designed 5/17/00 -06 m bga package outline diagram change 1/15/01 -07 tfbga package added cfi specification clarification 3/06/01 -08 document type : from preliminary data to data sheet 70ns speed class added 3/12/01 -09 4/13/01 -10 completely rewritten and restructured, 85ns speed class added. 5/29/01 -11 corrections made to cfi data. 31-may-2001 -12 corrections to tfbga46 package dimensions. 30-oct-2001 -13 v ddq maximum changed to 3.3v commands table, read cfi query address on 1st cycle changed to `x' (table 3) t whel description clarified (table 13) 16-may-2002 -14 v ddq maximum changed to 3.6v, tfbga and m bga package dimensions added to descriptions.
m28w160bt, m28w160bb 34/45 appendix a. block address tables table 22. top boot block addresses, m28w160bt table 23. bottom boot block addresses, m28w160bb # size (kword) address range 0 4 ff000-fffff 1 4 fe000-fefff 2 4 fd000-fdfff 3 4 fc000-fcfff 4 4 fb000-fbfff 5 4 fa000-fafff 6 4 f9000-f9fff 7 4 f8000-f8fff 8 32 f0000-f7fff 9 32 e8000-effff 10 32 e0000-e7fff 11 32 d8000-dffff 12 32 d0000-d7fff 13 32 c8000-cffff 14 32 c0000-c7fff 15 32 b8000-bffff 16 32 b0000-b7fff 17 32 a8000-affff 18 32 a0000-a7fff 19 32 98000-9ffff 20 32 90000-97fff 21 32 88000-8ffff 22 32 80000-87fff 23 32 78000-7ffff 24 32 70000-77fff 25 32 68000-6ffff 26 32 60000-67fff 27 32 58000-5ffff 28 32 50000-57fff 29 32 48000-4ffff 30 32 40000-47fff 31 32 38000-3ffff 32 32 30000-37fff 33 32 28000-2ffff 34 32 20000-27fff 35 32 18000-1ffff 36 32 10000-17fff 37 32 08000-0ffff 38 32 00000-07fff # size (kword) address range 38 32 f8000-ffff f 37 32 f0000-f7fff 36 32 e8000-effff 35 32 e0000-e7fff 34 32 d8000-dffff 33 32 d0000-d7fff 32 32 c8000-cffff 31 32 c0000-c7fff 30 32 b8000-bffff 29 32 b0000-b7fff 28 32 a8000-affff 27 32 a0000-a7fff 26 32 98000-9ffff 25 32 90000-97fff 24 32 88000-8ffff 23 32 80000-87fff 22 32 78000-7ffff 21 32 70000-77fff 20 32 68000-6ffff 19 32 60000-67fff 18 32 58000-5ffff 17 32 50000-57fff 16 32 48000-4ffff 15 32 40000-47fff 14 32 38000-3ffff 13 32 30000-37fff 12 32 28000-2ffff 11 32 20000-27fff 10 32 18000-1ffff 9 32 10000-17fff 8 32 08000-0ffff 7 4 07000-07fff 6 4 06000-06fff 5 4 05000-05fff 4 4 04000-04fff 3 4 03000-03fff 2 4 02000-02fff 1 4 01000-01fff 0 4 00000-00fff
35/45 m28w160bt, m28w160bb appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 24, 25, 26, 27, 28 and 29 show the addresses used to re- trieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 29, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read command to return to read mode. table 24. query structure overview note: query data are always presented on the lowest order data outputs. table 25. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are `0'. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description value 00h 0020h manufacturer code st 01h 0090h 0091h device code top bottom 02h-0fh reserved reserved 10h 0051h query unique ascii string oqryo aqo 11h 0052h query unique ascii string oqryo aro 12h 0059h query unique ascii string oqryo ayo 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm intel compatible 14h 0000h 15h offset = p = 0035h address for primary algorithm extended query table p=35h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists na 1ah 0000h
m28w160bt, m28w160bb 36/45 table 26. cfi query system interface information offset data description value 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7v 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6v 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.4v 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.6v 1fh 0004h typical timeout per single word program = 2 n m s 16 m s 20h 0004h typical timeout for double word program = 2 n m s 16 m s 21h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 0000h typical timeout for full chip erase = 2 n ms na 23h 0005h maximum timeout for word program = 2 n times typical 512 m s 24h 0005h maximum timeout for double word program = 2 n times typical 512 m s 25h 0003h maximum timeout per individual block erase = 2 n times typical 8s 26h 0000h maximum timeout for chip erase = 2 n times typical na
37/45 m28w160bt, m28w160bb table 27. device geometry definition offset word mode data description value 27h 0015h device size = 2 n in number of bytes 2mbyte 28h 29h 0001h 0000h flash device interface code description x16 async 2ah 2bh 0002h 0000h maximum number of bytes in multi-byte program or page = 2 n 4 2ch 0002h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 2 m28w160bt 2dh 2eh 001eh 0000h region 1 information number of identical-size erase block = 001eh+1 31 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase block = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8kbyte m28w160bb 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8kbyte 31h 32h 001eh 0000h region 2 information number of identical-size erase block = 001eh+1 31 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64kbyte
m28w160bt, m28w160bb 38/45 table 28. primary algorithm-specific extended query table note: 1. see table 25, offset 15h for p pointer definition. table 29. security code area offset p = 35h (1) data description value (p+0)h = 35h 0050h primary algorithm extended query table unique ascii string aprio opo (p+1)h = 36h 0052h oro (p+2)h = 37h 0049h oio (p+3)h = 38h 0031h major version number, ascii o1o (p+4)h = 39h 0030h minor version number, ascii o0o (p+5)h = 3ah 0006h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend (1 = yes, 0 = no) bit 3 lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 31 to 5 reserved; undefined bits are `0' no yes yes no no (p+6)h = 3bh 0000h (p+7)h = 3ch 0000h (p+8)h = 3dh 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are `0' yes (p+a)h = 3fh 0000h block lock status defines which bits in the block status register section of the query are implemented. bit 0 block lock status register lock/unlock bit active(1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are `0' na (p+b)h = 40h 0000h (p+c)h = 41h 0030h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 3v (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12v (p+e)h 0000h reserved offset data description 81h xxxx 64 bits unique device number. 82h xxxx 83h xxxx 84h xxxx
39/45 m28w160bt, m28w160bb appendix c. flowcharts and pseudo codes figure 20. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai03538b start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0x40) ; /*or writetoflash (any_address, 0x10) ; */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
m28w160bt, m28w160bb 40/45 figure 21. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h ai03539b start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (any_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
41/45 m28w160bt, m28w160bb figure 22. program suspend & resume flowchart and pseudo code write 70h ai03540b read status register yes no b7 = 1 yes no b2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b2==0) /*program completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
m28w160bt, m28w160bb 42/45 figure 23. erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. write 20h ai03541b start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1 v pp invalid error (1) command sequence error (1) no no b5 = 0 erase error (1) end yes no b1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (any_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.b7== 0) ; do { status_register=readflash (any_address) ; /* e or g must be toggled*/ if (status_register.b3==1) /*vpp invalid error */ error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; }
43/45 m28w160bt, m28w160bb figure 24. erase suspend & resume flowchart and pseudo code write 70h ai03549b read status register yes no b7 = 1 yes no b6 = 1 erase continues write d0h read data from another block or program start write b0h erase complete write ffh read data erase_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (any_address) ; /* e or g must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b6==0) /*erase completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume erase*/ } } write ffh
m28w160bt, m28w160bb 44/45 appendix d. command interface and program/erase controller state table 30. write state machine current/next note: elect.sg. = electronic signature. current state sr bit 7 data when read command inpu t (and next state) read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) program/ erase suspend (b0h) prog ram/ erase resume (d0h) read status (70h) clear status (50h) read elect.sg. (90h) read array a1o array read array program setup erase setup read array read status read array read elect.sg. read status a1o status read array program setup erase setup read array read status read array read elect.sg. read elect.sg. a1o electronic signature read array program setup erase setup read array read status read array read elect.sg. program setup a1o status program (command input = data to be programmed) program (continue) a0o status program (continue) program suspend to read status program (continue) program suspend to read status a1o status program suspend to read array program suspend to read array program (continue) program suspend to read array program (continue) program suspend to read status program suspend to read array program suspend to read elect.sg. program suspend to read array a1o array program suspend to read array program suspend to read array program (continue) program suspend to read array program (continue) program suspend to read status program suspend to read array program suspend to read elect.sg. program suspend to read elect.sg. a1o electronic signature program suspend to read array program suspend to read array program (continue) program suspend to read array program (continue) program suspend to read status program suspend to read array program suspend to read elect.sg. program (complete) a1o status read array program setup erase setup read array read status read array read elect.sg. erase setup a1o status erase command error erase (continue) erase command error erase (continue) erase command error erase cmd. error a0o status read array program setup erase setup read array read status read array read elect.sg. erase (continue) a1o status erase (continue) erase suspend to read status erase (continue) erase suspend to read status a1o status erase suspend to read array program setup erase suspend to read array erase (continue) erase suspend to read array erase (continue) erase suspend to read status erase suspend to read array erase suspend to read elect.sg. erase suspend to read array a1o array erase suspend to read array program setup erase suspend to read array erase (continue) erase suspend to read array erase (continue) erase suspend to read status erase suspend to read array erase suspend to read elect.sg. erase suspend to read elect.sg. a1o electronic signature erase suspend to read array program setup erase suspend to read array erase (continue) erase suspend to read array erase (continue) erase suspend to read status erase suspend to read array erase suspend to read elect.sg. erase (complete) a1o status read array program setup erase setup read array read status read array read elect.sg.
45/45 m28w160bt, m28w160bb information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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